System-on-chip for communications: the dawn of ASIPs and the dusk of ASICs

Summary form only given. ASIC designers have found that they can use less than half of the gates allowed by 90 nm technology. To make full use of the potential of semiconductor technology, a trend towards application specific SoCs will occur. A number of technical as well as economical reasons are responsible for this trend. We focus on SoCs for communication applications. The SoC can be viewed as software-definable, heterogeneous, multi-processor engine. A key role in the future will be played by ASIPs, which are jointly designed by algorithm and hardware architects. Moving from RT level ASIC design to coarse-grained ASIP building blocks is the logical result of a step up to a higher level of abstraction, comparable to the previous design revolution from gates to RTL. The design of ASIPs has become possible by new processor description languages, such as LISA, which contain the necessary information to synthesize automatically the instruction set and, at the same time, to generate the corresponding embedded software development environment including efficient HLL compilers. We conjecture that this fact will lead to a paradigm change in design methodology and will revolutionize the industry as it will enable system houses to use their IP optimally.