Title :
All Verilog mixed-signal simulator with analog behavioral and noise models
Author :
Mayes, M.K. ; Chin, S.W.
Author_Institution :
Nat. Semicond., Santa Clara, CA, USA
Abstract :
A full chip mixed-signal simulation method has been presented. An all Verilog simulation engine verified a 16-bit pipe-lined ADC design for functionality and noise performance. Fast simulation times and high accuracy were achieved using Verilog models for analog components and noise.
Keywords :
analogue-digital conversion; circuit analysis computing; hardware description languages; integrated circuit modelling; integrated circuit noise; mixed analogue-digital integrated circuits; 16 bit; all Verilog simulation engine; analog components; behavioral model; full chip mixed-signal simulation; noise model; pipelined ADC design; Engines; Hardware design languages;
Conference_Titel :
VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-3339-X
DOI :
10.1109/VLSIC.1996.507765
