A frequency channelized adaptive wideband receiver for high-speed links

A new class of high-speed link receiver architecture that operates at a fraction of the on-chip clock frequency is proposed. Instead of time-interleaving multiple ADCs as is conventionally done, the received signal is channelized into multiple frequency subbands using a bank of mixers and lowpass filters. The proposed receiver architecture enjoys numerous implementation advantages. Based on the frequency channelized signals, an adaptive synchronization/detection scheme is described. An adaptive solution is necessary since the propagation channel and the analog analysis filters are generally not perfectly known and the symbol rate is incommensurate with the free running ADC sampling rate.