• DocumentCode
    2126595
  • Title

    A dual layer bitline DRAM array with Vcc/Vss hybrid precharge for multi-gigabit DRAMs

  • Author

    Nakano, H. ; Takashima, D. ; Tsuchida, K. ; Shiratake, S. ; Inaba, T. ; Ohta, M. ; Oowaki, Y. ; Watanabe, S. ; Ohuchi, K. ; Matsunaga, J.

  • Author_Institution
    ULSI Res. Center, Toshiba Corp., Kawasaki, Japan
  • fYear
    1996
  • fDate
    13-15 June 1996
  • Firstpage
    190
  • Lastpage
    191
  • Abstract
    A dual layer BL array and a Vcc/Vss hybrid precharge sensing scheme has been proposed. The array affords the maximum memory cell density and relaxed sense amplifier layout which is as wide as the conventional folded BL sense amplifier layout. The Vcc/Vss hybrid precharge scheme gives the doubled operation voltage for sensing compared with the conventional half Vcc precharge method without the BL charge/discharge current increase.
  • Keywords
    CMOS memory circuits; DRAM chips; VLSI; Vcc/Vss hybrid precharge; dual layer bitline DRAM array; multi-gigabit DRAMs; precharge sensing scheme; sense amplifier layout; Random access memory; Variable structure systems; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on
  • Conference_Location
    Honolulu, HI, USA
  • Print_ISBN
    0-7803-3339-X
  • Type

    conf

  • DOI
    10.1109/VLSIC.1996.507766
  • Filename
    507766
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2126595