DocumentCode
2126634
Title
Flexible test mode design for DRAM characterization
Author
Wong, Hang ; Kirihata, Toshiaki ; DeBrosse, J. ; Watanabe, Yoshihiro ; Hara, Tenshi ; Yoshida, Manabu ; Wordeman, M. ; Fujii, Shohei ; Krsnik, B.
Author_Institution
Semicond. Res. & Dev. Center, IBM Corp., Hopewell Junction, NY, USA
fYear
1996
fDate
13-15 June 1996
Firstpage
194
Lastpage
195
Abstract
Testing is a crucial process in the development and production of VLSI memory chips. On-chip test modes not only reduce manufacturing test time, but also allow effective debugging of the technology during the development phase. This paper describes the flexible test modes deployed in our fully functional 256 Mb DRAM chip.
Keywords
DRAM chips; VLSI; integrated circuit testing; production testing; 256 Mbit; DRAM characterization; VLSI memory chips; debugging; development phase; flexible test mode design; manufacturing test time; on-chip test modes; Debugging; Manufacturing; Production; Random access memory; Testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on
Conference_Location
Honolulu, HI, USA
Print_ISBN
0-7803-3339-X
Type
conf
DOI
10.1109/VLSIC.1996.507768
Filename
507768
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