Subword parallel GF(2m) ALU: an implementation for a cryptographic processor

The paper describes a subword parallel ALU for applications which require operations over GF(2^m) and an implementation in the domain of cryptography. It has a reconfigurable datapath that allows it to operate in either a single instruction multiple data mode (SIMD, p GF(2^r) operations, where r≤q) or a single instruction single data mode (SISD, one GF(2^r) operation, where qm) arithmetic, but have a large data size mismatch) on the same processor. This means better resource utilization of the processor which is doubly important for area constrained implementations. An FPGA prototype of the processor has been built and tested successfully for AES and elliptic curve operations.