Title :
A Ti salicide process for 0.10 /spl mu/m gate length CMOS technology
Author :
Kittl, J.A. ; Qi-Zhong Hong ; Redder, M. ; Prinslow, D.A. ; Misium, G.R.
Author_Institution :
Semicond. Process & Device Center, Texas Instrum. Inc., Dallas, TX, USA
Abstract :
The fundamental issues for extension of a Ti salicide process to 0.1 /spl mu/m gate length CMOS technologies are presented for the first time. We report the first process to achieve low sheet resistance of 4 /spl Omega//sq at an ultra-narrow 0.10 /spl mu/m gate length (with deposited Ti=27 nm for TiSi/sub 2/=50 nm). Successful implementation into a sub-0.18 /spl mu/m gate length CMOS technology is demonstrated.
Keywords :
CMOS integrated circuits; VLSI; integrated circuit measurement; integrated circuit metallisation; titanium compounds; 0.1 micron; CMOS technology; TiSi/sub 2/; salicide process; sheet resistance; ultra-narrow gate length; CMOS process; CMOS technology;
Conference_Titel :
VLSI Technology, 1996. Digest of Technical Papers. 1996 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-3342-X
DOI :
10.1109/VLSIT.1996.507775
