A high performance configurable random divider with FGPA and ASIC implementation

The divider is the one of the most important modules in microprocessors. A new algorithm was proposed to realize the decimal frequency divider with any number divide ratio, and the divide ratio was configurable by the SPI. In the statistical periods, the divide ratio is adjusted dynamically by calculating the error of clock. Error of divider can be reduced, and the accuracy after the four rounds has come to 1E-14% after 4 rounds. The implementation of decimal frequency divider was realized with FPGA and ASIC (under 180nm technology). The experimental result indicated that the decimal frequency divider takes fewer resources, and its performance is steady and reliable.