A stack capacitor technology with (Ba,Sr)TiO/sub 3/ dielectrics and Pt electrodes for 1 Giga-Bit density DRAM

Author

Soon Oh Park ; Cheol Seong Hwang ; Chang-Suk Kang ; Hag-Ju Cho ; Byoung Teak Lee ; Won Jong Yoo ; Young So Park ; Sang In Lee ; Moon Yong Lee

Author_Institution

Semicond. R&D Center, Samsung Electronics Co. Ltd., Kyunki, South Korea

fYear

1996

fDate

11-13 June 1996

Firstpage

24

Lastpage

25

Abstract

(Ba,Sr)TiO/sub 3/ (BST) capacitors with Pt electrode are fabricated on SiO/sub 2//Si substrates by sputtering method. Although BST is known to have a large dielectric constant, it decreases with decreasing film thickness. Therefore, it requires a serious process optimization to obtain small enough t/sub oxeq/. A sputtering process which produces BST film with t/sub oxeq/ of 0.24 nm is developed in this study. A DRAM capacitor fabrication technology with 0.46 /spl mu/m pitch is also developed with proper techniques of etching of Pt and deposition of sputter BST or MOCVD SrTiO/sub 3/ films.

Keywords

DRAM chips; barium compounds; integrated circuit technology; platinum; sputter deposition; strontium compounds; thin film capacitors; (BaSr)TiO/sub 3/-Pt; 1 Gbit; DRAM fabrication; MOCVD SrTiO/sub 3/ film; Pt electrode; SiO/sub 2/-Si; SiO/sub 2//Si substrate; dielectric constant; etching; process optimization; sputtered BST film; stack capacitor technology; Binary search trees; Capacitors; Dielectric constant; Dielectric substrates; Electrodes; Fabrication; MOCVD; Random access memory; Sputter etching; Sputtering;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1996. Digest of Technical Papers. 1996 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-3342-X

Type

conf

DOI

10.1109/VLSIT.1996.507779

Filename

507779