Area-efficient high-throughput VLSI architecture for MAP-based turbo equalizer

We present an area-efficient MAP-based turbo equalizer VLSI architecture by proposing a symbol-based soft-input soft-output (SISO) kernel which processes one multi-bit symbol in every clock cycle. The symbol-based SISO hardware can be shared by the equalizer and decoder, thereby reducing silicon area. Further, by introducing block-interleaved computation in the add-compare-select recursions, the critical path delay is reduced, thereby improving throughput. Experimental results with QPSK modulation and K⊃5 encoder demonstrate that the proposed area-efficient architecture achieves area savings of 47% with 11% throughput gain in a 0.25 μm CMOS process. It is also shown that the throughput is improved by 79% via block-interleaved computation with an area savings of 25%.