A gate-side air-gap structure (GAS) to reduce the parasitic capacitance in MOSFETs

A new parasitic capacitance reduction technologies, utilizing a Gate-side Air-gap Structure (GAS), has been developed for MOSFETs. The GAS in which a 5-nm-wide air-gap was formed next to the gate reduced the fringe capacitance by half. Hence, the gate delay time was reduced by 4.8 psec at FO=1 and by 16 psec at FO=3 in a 0.25 /spl mu/m CMOS, and power consumption was lowered compared to a conventional structure. We also propose pocket implantation through the GAS to suppress short channel effects with only a slight increase in the junction capacitance.