VLSI implementation of multiplier-free low power baseband filter for CDMA systems

A multiplier-free baseband filter is proposed for the low power VLSI implementation in a code division multiple access (CDMA) system. The new computational efficient filter structure is based on a novel prefilter structure involving a pair of even and odd length FIR filters with the same band edges. It is shown by example that the new structure not only achieves 45.8% savings in the number of multipliers, but also reduces the word length requirement for the coefficients of an IS-95 CDMA baseband filter. The VLSI implementation shows that the new structure reduces both the chip area and power consumption considerably compared with the direct-form implementation.