Reconfigurable discrete wavelet transform architecture for advanced multimedia systems

A novel reconfigurable discrete wavelet transform architecture is proposed to meet the diverse computing requirements of advanced multimedia systems. The proposed architecture mainly consists of a reconfigurable processing element array and a reconfigurable address generator, featuring a dynamically reconfigurable capability where the wavelet filter kernels and wavelet decomposition structures can be reconfigured at run-time with little overhead. The lifting-based reconfigurable processing element array possesses better computational efficiency than a convolution-based architecture, and a systematic design method is provided to generate the hardware configurations of different wavelet filter kernels for it. The reconfigurable address generator handles flexible address generation for data I/O access in different wavelet decomposition structures. A prototyping chip has been fabricated by the TSMC 0.35 μm 1P4M CMOS process, and, at 50 MHz, it can achieve at most 100 Mpixel/sec transform throughput, proving it to be a universal and extremely flexible computing engine for advanced multimedia systems.