Advanced ion implantation and rapid thermal annealing technologies for highly reliable 0.25 /spl mu/m dual gate CMOS

Author

Shimizu, S. ; Kuroi, T. ; Kawasaki, Y. ; Tsutsumi, T. ; Oda, H. ; Inuishi, M. ; Miyoshi, H.

Author_Institution

ULSI Lab., Mitsubishi Electr. Corp., Itami, Japan

fYear

1996

fDate

11-13 June 1996

Firstpage

64

Lastpage

65

Abstract

Advanced ion implantation and rapid thermal annealing technologies are proposed to realize highly reliable 0.25 /spl mu/m salicided dual gate CMOS for high performance logic application. These technologies mainly consist of mixing the CoSi/sub 2//Si interface using silicon implantation, CVD-Si/sub 3/N/sub 4//CVD-SiO/sub 2/ sidewall spacer, nitrogen implantation in gate polysilicon and source/drain regions and rapid thermal annealing (RTA) for reduction of thermal budget.

Keywords

CMOS logic circuits; chemical vapour deposition; cobalt compounds; elemental semiconductors; integrated circuit metallisation; ion implantation; rapid thermal annealing; silicon; 0.25 micron; CoSi/sub 2/-Si; gate polysilicon region; high performance logic application; ion implantation; rapid thermal annealing; salicided dual gate CMOS; sidewall spacer; source/drain region; thermal budget; CMOS logic circuits; CMOS technology; Ion implantation; Nitrogen; Rapid thermal annealing; Silicon; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1996. Digest of Technical Papers. 1996 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-3342-X

Type

conf

DOI

10.1109/VLSIT.1996.507795

Filename

507795