A 0.25 /spl mu/m gate length CMOS technology for 1V low power applications-device design and power/performance considerations

Device design issues in optimizing a 0.25 /spl mu/m gate length CMOS technology with multiple V/sub t/ s for 1V low power applications are studied. For the low-V/sub t/ transistor design, counterdoped super-steep retrograde (SSR+CD) channel profile is demonstrated as the optimum choice compared to the other channel profiles studied, viz. counterdoped pocket (Pocket+CD), counterdoped conventional (Conv.+CD),and conventional (Conv.), because of its superior V/sub t/-rolloff, higher nominal drive current (I/sub DRIVE/), nominal gate length being shorter than the target 0.25 /spl mu/m, and lower sensitivity of I/sub DRIVE/ to gate length control (/spl Delta/L/sub G/). The measured inverter delays and power-performance tradeoffs for both the low- and high-V/sub t/ CMOS compare favorably with the published data. For L/sub G/=0.2 /spl mu/m, the inverter delays are 60 and 32 psec/stage at IV for high-V/sub t/ and low-V/sub t/ CMOS, respectively. Additional device design issues viz. effect of gate sheet resistance (/spl rho//sub sh/), V/sub t/ and V/sub cc/ on the fraction of active power (P/sub a/) wasted as short power (P/sub s/) are investigated. High /spl rho//sub sh/ is shown, for the first time, to increase the P/sub s/. The effects of lowering V/sub cc/ and V/sub t/ (to reduce power and gain performance) on P/sub s/ depend on circuit applications: for signal-line driver (single inverter with fixed slewrate for input signal) lowering V/sub cc/ greatly reduces the P/sub s//P/sub a/. However, in logic circuits (represented by FO=4 inverter chains) the corresponding change in P/sub s//P/sub a/ is small. In both circuits lowering the V/sub t/ below /spl sim/0.1 V can greatly increase the P/sub s/. These findings may impact the design rules for 1 V ultra-low power circuits.