Manufacturable and reliable fluorine-doped low-k interlayer dielectric process for high performance logic LSI

Author

Igarashi, H. ; Oyamatsu, H. ; Kodera, M. ; Kaji, N. ; Matsuno, T. ; Shibata, I. ; Kinugawa, M. ; Kakumu, M.

Author_Institution

Semicond. Device Eng. Lab., Toshiba Corp., Kawasaki, Japan

fYear

1996

fDate

11-13 June 1996

Firstpage

84

Lastpage

85

Abstract

Advanced process integration with low-k fluorine-doped interlayer dielectric was presented. Performance improvement due to wiring capacitance reduction was confirmed from speed analysis of inverter delay time by 7%. And it was clarified that there was no influence of fluorine in interlayer dielectric to MOSFET´s reliability. This process was carefully optimized from total CMOS integration point of view and was applied to development and production of advanced logic LSI.

Keywords

CMOS logic circuits; fluorine; integrated circuit interconnections; integrated circuit reliability; large scale integration; permittivity; CMOS integration; MOSFET reliability; SiO/sub 2/:F; fluorine-doped low-k interlayer dielectric process; inverter delay time; logic LSI; manufacture; relative dielectric constant; wiring capacitance; CMOS logic circuits; CMOS process; Capacitance; Delay effects; Dielectrics; Inverters; Manufacturing; Performance analysis; Production; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1996. Digest of Technical Papers. 1996 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-3342-X

Type

conf

DOI

10.1109/VLSIT.1996.507802

Filename

507802