• DocumentCode
    2127616
  • Title

    Estimating test cost during data path and controller synthesis with low power overhead

  • Author

    Harmanani, Haidar M. ; Kodeih, Maya

  • Author_Institution
    Dept. of Comput. Sci. & Math., Lebanese American Univ., Byblos, Lebanon
  • fYear
    2010
  • fDate
    2-5 May 2010
  • Firstpage
    1
  • Lastpage
    5
  • Abstract
    This paper presents a method for concurrent BIST cost estimation during testable data path allocation. The method integrates testability in the design process and generates a distributed test controller that aims to minimize area and power. The system has been implemented and favorable results are reported.
  • Keywords
    circuit testing; control engineering computing; control system synthesis; costing; data flow graphs; high level synthesis; concurrent BIST cost estimation; controller synthesis; data path synthesis; distributed test controller; low power overhead; Built-in self-test; Clocks; Finite impulse response filter; Kernel; Logic gates; Registers; Resource management;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical and Computer Engineering (CCECE), 2010 23rd Canadian Conference on
  • Conference_Location
    Calgary, AB
  • ISSN
    0840-7789
  • Print_ISBN
    978-1-4244-5376-4
  • Electronic_ISBN
    0840-7789
  • Type

    conf

  • DOI
    10.1109/CCECE.2010.5575139
  • Filename
    5575139
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2127616