High performance SEED processors

Author

Choi, Hong-mook ; Cho, Hwa-hyun ; Lee, Sang-kil ; Choi, Myung-qul

Author_Institution

Dept. of EECI, Hanyang Univ., Seoul, South Korea

fYear

2003

fDate

27-29 Aug. 2003

Firstpage

269

Lastpage

274

Abstract

Currently, information security is an important issue in our information society and technology. We propose two efficient architectures for processing the 128 bit SEED block cipher using a 32 bit data bus. We compare the proposed architectures with the conventional SEED processor. The proposed SEED processors improve speed and reduce hardware resources using only one G-function in the F-function and the key scheduler of SEED. The operation of the proposed methods has been verified with functional simulation, synthesis and tested on board. The proposed architecture is suitable for hardware-critical applications, such as smart card, PDA, mobile phone, etc.

Keywords

cryptography; logic design; signal processing; 128 bit; 32 bit; F-function; G-function; PDA; SEED block cipher; SEED processors; cryptography; information security; key scheduler; mobile phone; smart card; symmetric key block cipher; Application specific integrated circuits; Computer crime; Cryptography; Data security; Field programmable gate arrays; Hardware; Process design; Real time systems; Software algorithms; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems, 2003. SIPS 2003. IEEE Workshop on

ISSN

1520-6130

Print_ISBN

0-7803-7795-8

Type

conf

DOI

10.1109/SIPS.2003.1235681

Filename

1235681