CMOS interleaved distributed 2 × 3 matrix amplifier employing active post distortion and optimum gate bias linearization technique

In this paper, the design of a fully-integrated CMOS interleaved distributed 2 × 3 matrix amplifier employing active post distortion and optimum gate bias linearization technique that allows for broadband distortion reduction is presented. Simulation results has yielded a peak S₂₁ power gain of 7.1 dB and then rolls off to a unity gain bandwidth of 16 GHz with less than -10 dB return loss and S₁₂ Isolation less than -45 dB. The simulation results show a 9 dBm IIP3 improvement corresponding to a third-order intermodulation IM3 suppression of 18 dB improvement at output power of -10 dBm. The proposed linearized interleaved distributed 2 × 3 matrix amplifier was designed using the 0.13 μm CMOS technology.