Title :
0.2 /spl mu/m analog CMOS with very low noise figure at 2 GHz operation
Author :
Ohgaro, T. ; Morifuji, E. ; Saito, M. ; Ono, M. ; Yoshitomi, T. ; Momose, H.S. ; Ito, N. ; Iwai, H.
Author_Institution :
ULSI Res. Labs., Toshiba Corp., Kawasaki, Japan
Abstract :
Reduction of the noise figure of silicon MOSFETs at 2 GHz operation has been investigated. It was confirmed that reduction in gate length and the resistances of source and drain are effective to reduce the noise. There is very small difference in the fT value of Ni- and Ti-salicide MOSFETs, but NFmin was significantly smaller in the Ni case that that of Ti. Very small NFmin values of 0.6 dB and 1.4 dB for n- and p-MOSFETs, respectively, with Lf=5 /spl mu/m and Wg=200 /spl mu/m were obtained for the first time by using 0.2 /spl mu/m Ni-salicide CMOS technology. Power consumption of this n-MOSFET to obtain the NFmin value of 1 dB reduced significantly to 1/8 of that of without Ni-salicide. These results suggest a high possibility of deep-submicron CMOS for application into RF frontend telecommunication ICs which have been conventionally produced by using mainly III-V devices.
Keywords :
CMOS analogue integrated circuits; MOSFET; VLSI; integrated circuit measurement; integrated circuit noise; integrated circuit technology; 0.2 micron; 0.6 dB; 1.4 dB; 2 GHz; MOSFETs; RF frontend telecommunication ICs; analog CMOS; deep-submicron CMOS; drain resistance; gate length; noise figure; salicide CMOS technology; source resistance; CMOS technology; Energy consumption; III-V semiconductor materials; MOSFET circuits; Noise figure; Noise reduction; Radio frequency; Silicon;
Conference_Titel :
VLSI Technology, 1996. Digest of Technical Papers. 1996 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-3342-X
DOI :
10.1109/VLSIT.1996.507821
