A Multitier Study on Various Stacking Topologies of TSV-Based PDN Systems Using On-Chip Decoupling Capacitor Models

We studied the impedance characteristics of through-silicon via (TSV)-based power delivery networks (PDNs) for hierarchical on-die simulation and interconnect noise analysis. This paper compares the quality of power delivery in 3-D stacking scenarios for three distinct chip stacking topologies: 1) face-to-back (F2B); 2) face-to-face (F2F); and 3) back-to-back (B2B). Quantitatively, this paper compared the impedance noise level between the three stacking topologies and found the PDN impedance noise of F2F chip stacking to be relatively lower than F2B and B2B chip stacking topologies. A power delivery impedance below 1 Ω for F2F chip stacking topology was possible up to 2 GHz. However, for F2B and B2B chip stacking, the PDN impedance could not get beyond sub-1 Ω. The impedance was simulated between 0.1 and 20 GHz. Among power grid and power and ground TSV models presented in this paper, we also present and implemented a metal-insulator-metal capacitor model written as a complex impedance equation. With capacitor dimensions similar to the unit cell gird size (200 μm × 200 μm), the capacitance density (per unit area) ranged from 0.062 pF/μm² to 5.325 fF/μm².