Title :
A symmetric diagonal driver transistor SRAM cell with imbalance suppression technology for stable low voltage operation
Author :
Horiba, S. ; Takahashi, T. ; Ohkubo, H. ; Noda, K. ; Hayashi, F. ; Uchida, T. ; Yokoyama, T. ; Ando, K. ; Yoshida, T. ; Hashimoto, T. ; Shimizu, T.
Author_Institution :
ULSI Device Dev. Labs., NEC Corp., Kanagawa, Japan
Abstract :
A symmetric diagonal driver transistor (SDDT) cell has been developed for low voltage SRAM operation which exhibits high alignment tolerance. This new symmetric cell layout substantially suppresses the imbalance in a pair of cell transistor characteristics and, combined with silicon nitride self-aligned contact (Si/sub 3/N/sub 4/-SAC) and low resistance ground-line structures, results in a minimum operation voltage of 1.9 V, which is 0.3 V lower than that of the conventional split word line cell.
Keywords :
SRAM chips; integrated circuit technology; 1.9 V; Si/sub 3/N/sub 4/; alignment tolerance; ground-line structure; imbalance suppression technology; low voltage operation; silicon nitride self-aligned contact; symmetric diagonal driver transistor SRAM cell; Contact resistance; Driver circuits; Low voltage; Random access memory; Silicon;
Conference_Titel :
VLSI Technology, 1996. Digest of Technical Papers. 1996 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-3342-X
DOI :
10.1109/VLSIT.1996.507826
