A symmetric diagonal driver transistor SRAM cell with imbalance suppression technology for stable low voltage operation

A symmetric diagonal driver transistor (SDDT) cell has been developed for low voltage SRAM operation which exhibits high alignment tolerance. This new symmetric cell layout substantially suppresses the imbalance in a pair of cell transistor characteristics and, combined with silicon nitride self-aligned contact (Si/sub 3/N/sub 4/-SAC) and low resistance ground-line structures, results in a minimum operation voltage of 1.9 V, which is 0.3 V lower than that of the conventional split word line cell.