Title :
A 5-/spl mu/m/sup 2/ full-CMOS cell for high-speed SRAMs utilizing a optical-proximity-effect correction (OPC) technology
Author :
Ueshima, M. ; Mano, M. ; Yoneda, Y. ; Ichikawa, T. ; Tsudaka, K. ; Takahashi, H. ; Yamamura, I. ; Yabuta, M. ; Motoyoshi, M.
Author_Institution :
MOS LSI Div., Sony Corp., Kanagawa, Japan
Abstract :
A 5.01-/spl mu/m/sup 2/ full-CMOS SRAM cell using a 0.28-/spl mu/m design rule has been developed and the cell operation at as low as 0.6 V was confirmed. This cell has been designed not only to be small but also to be widened bitline pitch for reduction of bitline delay. To realize this cell, optical-proximity-effect correction (OPC) and some technologies for cell-size reduction have been adopted. In addition, glue layer wiring (GLAW) for the local interconnection has been used in order to simplify the process.
Keywords :
CMOS memory circuits; SRAM chips; integrated circuit interconnections; photolithography; proximity effect (lithography); 0.28 micron; 0.6 V; bitline delay; bitline pitch; full-CMOS cell; glue layer wiring; high-speed SRAM; local interconnection; optical-proximity-effect correction technology; Delay; Optical interconnections; Random access memory; Wiring;
Conference_Titel :
VLSI Technology, 1996. Digest of Technical Papers. 1996 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-3342-X
DOI :
10.1109/VLSIT.1996.507827
