A high-performance 0.08 /spl mu/m CMOS

Author

Su, L. ; Subbanna, S. ; Crabbe, E. ; Agnello, P. ; Nowak, E. ; Schulz, R. ; Rauch, S. ; Ng, H. ; Newman, T. ; Ray, A. ; Hargrove, M. ; Acovic, A. ; Snare, J. ; Crowder, S. ; Chen, B. ; Sun, J. ; Davari, B.

Author_Institution

Semicond. Res. & Dev. Center, IBM Corp., Hopewell Junction, NY, USA

fYear

1996

fDate

11-13 June 1996

Firstpage

12

Lastpage

13

Abstract

We demonstrate a 0.08 /spl mu/m CMOS suitable for high-performance (V/sub dd/=1.8 V) and low-power applications (V/sub dd/<1.5 V) with the best current drive at a given off-current reported in the literature to date. Excellent short-channel effects were obtained for L/sub eff/ down to 0.06 /spl mu/m in the NFET and 0.08 /spl mu/m in the PFET. Aggressive lateral and vertical dopant engineering allow the VT to be reduced with no degradation in short-channel effects resulting in a 50% improvement in delay at V/sub dd/=1 V over the regular-V/sub T/ process.

Keywords

CMOS integrated circuits; VLSI; integrated circuit design; integrated circuit technology; semiconductor doping; 0.08 micron; 1.5 to 1.8 V; CMOS; NFET; PFET; current drive; delay; lateral dopant engineering; low-power applications; off-current; short-channel effects; vertical dopant engineering; Degradation; Delay effects;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1996. Digest of Technical Papers. 1996 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-3342-X

Type

conf

DOI

10.1109/VLSIT.1996.507838

Filename

507838