0.15 /spl mu/m delta-doped CMOS with on-field source/drain contacts

Author

Imai, K. ; Hu, C. ; Andoh, T. ; Kinoshita, Y. ; Matsubara, Y. ; Tatsumi, T. ; Yamazaki, T.

Author_Institution

ULSI Device Dev. Labs., NEC Corp., Kanagawa, Japan

fYear

1996

fDate

11-13 June 1996

Firstpage

172

Lastpage

173

Abstract

A delta-doped CMOS with on-field source/drain contacts is developed. After BF/sub 2/ and As ion implantation for NMOS and PMOS regions, non-doped selective epitaxial channel layer is grown by UHV-CVD, and polysilicon S/D electrodes deposited on the field are connected with the epitaxial channel layer simultaneously. This structure can reduce the source/drain parasitic junction capacitance similar to that of SOI CMOS. The inverter speed of the delta-doped CMOS with on-field source/drain contacts are 30% faster than that of the conventional CMOS.

Keywords

CMOS integrated circuits; capacitance; doping profiles; integrated circuit technology; ion implantation; vapour phase epitaxial growth; 0.15 micron; As ion implantation; BF/sub 2/ ion implantation; Si:As; Si:BF/sub 2/; UHV-CVD; delta-doped CMOS; epitaxial channel layer; nondoped selective epitaxial channel layer; onfield source/drain contacts; parasitic junction capacitance reduction; polysilicon S/D electrodes; source/drain parasitic junction capacitance; Electrodes; Inverters; Ion implantation; MOS devices; Parasitic capacitance;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1996. Digest of Technical Papers. 1996 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-3342-X

Type

conf

DOI

10.1109/VLSIT.1996.507840

Filename

507840