Ultra-shallow in-situ-doped raised source/drain structure for sub-tenth micron CMOS

Author

Nakahara, Y. ; Takeuchi, K. ; Tatsumi, T. ; Ochiai, Y. ; Manako, S. ; Samukawa, S. ; Furukawa, A.

Author_Institution

Microelectron. Res. Labs., NEC Corp., Kanagawa, Japan

fYear

1996

fDate

11-13 June 1996

Firstpage

174

Lastpage

175

Abstract

A new raised source/drain (RSD) structure is proposed, which combines facet controlled in-situ-doped selective Si epitaxial growth (SEG) and solid-phase diffusion (SPD). This can provide ultra-shallow junctions without sacrificing the parasitic resistance or capacitance. 0.1 /spl mu/m pMOSFETs with 20 nm deep junctions exhibiting excellent electrical characteristics and reliability were demonstrated. CMOS process compatibility was also confirmed.

Keywords

CMOS integrated circuits; MOSFET; diffusion; ion implantation; rapid thermal annealing; semiconductor device reliability; vapour phase epitaxial growth; 0.1 mum; 20 nm; BF/sub 2//sup +/ implantation; CMOS process compatibility; RTA; Si:B-SiO/sub 2/-SiN; electrical characteristics; facet controlled in-situ-doped selective Si epitaxial growth; pMOSFETs; parasitic resistance; reliability; short channel behavior; solid-phase diffusion; ultra-high vacuum CVD; ultra-shallow in-situ-doped raised source/drain structure; ultra-shallow junctions; CMOS process; Electric resistance; Electric variables; Epitaxial growth; MOSFETs; Parasitic capacitance;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1996. Digest of Technical Papers. 1996 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-3342-X

Type

conf

DOI

10.1109/VLSIT.1996.507841

Filename

507841