Instruction set extension in the NIOS II: A floating point divider for complex numbers

As increasing the clock frequency leads to unmanageable heat and power dissipation the search is on for another way to get more power efficient and faster embedded systems. Given that chip area is also a constraint, we investigate the addition of a custom instruction to the processor instruction set which enables the execution of an efficient complex division. The instruction we designed is a hardware divider for complex numbers which receives four input values and returns two output values. The data bandwidth constraint of 2 inputs and 1 output is loosened by making the instruction multicycle as described in previous work. We uses the custom instruction interface of the NIOS II soft processor and achieve a speedup of up to 3x over the unmodified instruction set.