Title :
ESD design for deep submicron SOI technology [NMOS transistor]
Author :
Duvvury, C. ; Amerasekera, A. ; Joyner, K. ; Ramaswamy, S. ; Young, S.
Author_Institution :
Semicond. Process & Device Center, Texas Instrum. Inc., Dallas, TX, USA
Abstract :
This paper establishes the critical ESD design issues for a partially depleted 0.35 /spl mu/m SOI process. Through device analysis we show for the first time that the gate bias of an NMOS during ESD plays a critical role in reducing channel heating and in achieving good protection levels for both positive and negative stress polarities. With an optimum design window, we demonstrate greater than /spl plusmn/2 kV ESD performance with no additional process steps.
Keywords :
MOSFET; electrostatic discharge; protection; silicon-on-insulator; 0.35 mum; 2 kV; ESD design; NMOS transistor; channel heating; deep submicron SOI technology; device analysis; gate bias; human body model; negative stress polarity; optimum design window; partially depleted SOI process; positive stress polarity; protection levels; Electrostatic discharge; Heating; MOS devices; MOSFETs; Protection; Stress;
Conference_Titel :
VLSI Technology, 1996. Digest of Technical Papers. 1996 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-3342-X
DOI :
10.1109/VLSIT.1996.507849
