DocumentCode :
2128696
Title :
Sub-quarter-micron dual gate CMOSFETs with ultra-thin gate oxide of 2 nm
Author :
Kuroi, T. ; Shimizu, S. ; Ogino, S. ; Teramoto, A. ; Shirahata, M. ; Okumura, Y. ; Inuishi, M. ; Miyoshi, H.
Author_Institution :
ULSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
fYear :
1996
fDate :
11-13 June 1996
Firstpage :
210
Lastpage :
211
Abstract :
The high performance 0.25 /spl mu/m dual gate CMOS with ultrathin gate oxide of 2 nm is demonstrated for low-voltage logic application. The boron penetration can effectively be suppressed by the nitrogen implantation technique, even if the gate oxide film is reduced to 2 nm. Moreover the inverter delay with an Al interconnect load can be remarkably improved by the highly drivable MOSFETs with thin gate oxide for low-voltage operation. Furthermore, the hot carrier degradation of NMOSFETs can be suppressed as reducing the oxide thickness. However it is found that the hot-carrier degradation of PMOSFETs is enhanced in thin-oxide region under channel hot-hole injection.
Keywords :
CMOS logic circuits; MOSFET; VLSI; delays; hot carriers; integrated circuit reliability; ion implantation; 0.25 micron; 2 nm; Al; Al interconnect load; B penetration suppression; LV operation; N implantation technique; NMOSFETs; PMOSFETs; Si:B; Si:N; channel hot-hole injection; dual gate CMOSFETs; gate oxide film; hot carrier degradation reduction; inverter delay; low-voltage logic application; sub-quarter-micron gate; ultra-thin gate oxide; Boron; CMOS logic circuits; CMOSFET logic devices; Degradation; Delay; Hot carriers; Inverters; MOSFETs; Nitrogen;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology, 1996. Digest of Technical Papers. 1996 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-3342-X
Type :
conf
DOI :
10.1109/VLSIT.1996.507853
Filename :
507853
Link To Document :
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