Boron sidewall implantation and selective etching of p-doped poly-Si for 1 Gbit DRAM stacked capacitors

It is generally accepted that a minimum cell capacitance of about 25 fF is necessary for DRAMs. In order to allow for lateral shrinking of the cell sizes while keeping the required cell capacitance, either trench or stacked capacitors cell concepts were proposed to provide the desired area magnification. Stack type capacitors are formed by taking advantage of different etch rates of various layers of oxides, oxides and poly-Si, or doped/undoped poly-Si. In this work, the authors describe a new process sequence to produce a stacked capacitor which meets the requirements for the production of 1 Gbit DRAMs. They demonstrate the feasibility of fin stack capacitors with mechanically supported fins produced by sidewall implantation and selective etching of p-doped poly-Si. The concept is scaleable to sizes required for 1 Gbit DRAMs.