A manufacturable 0.30 /spl mu/m gate CMOS technology for high speed microprocessors

Author

Appel, A. ; Crank, S. ; Kim, Y. ; Scharrer, C. ; Spratt, D. ; Strong, B. ; Yao, M. ; Tigelaar, H. ; Melanson, R.

Author_Institution

DPI Productization Facility, Texas Instrum. Inc., Dallas, TX, USA

fYear

1996

fDate

11-13 June 1996

Firstpage

220

Lastpage

221

Abstract

A 0.30 /spl mu/m gate CMOS technology for high speed microprocessors with five levels of interconnect is described. A primary challenge in developing a manufacturable 0.30 /spl mu/m gate CMOS process is gate length control. A detailed investigation of the sources of gate length variation using a specially designed testchip is presented. Linewidth control of /spl plusmn/10% is achieved using I-line lithography by applying optical proximity correction to the gate reticle. A high speed cache memory for the target 250 MHz microprocessor product has an access time of 2.02 ns from clock to data out.

Keywords

CMOS digital integrated circuits; integrated circuit manufacture; integrated circuit technology; microprocessor chips; photolithography; proximity effect (lithography); 0.3 micron; 2.02 ns; 250 MHz; I-line lithography; Si; five level interconnect; gate length control; gate reticle; high speed cache memory; high speed microprocessors; linewidth control; manufacturable CMOS technology; optical proximity correction; polysilicon gate process; submicron gate; CMOS process; CMOS technology; Cache memory; High speed optical techniques; Lithography; Manufacturing processes; Microprocessors; Optical control; Optical interconnections; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1996. Digest of Technical Papers. 1996 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-3342-X

Type

conf

DOI

10.1109/VLSIT.1996.507857

Filename

507857