Impact of cell threshold voltage distribution in the array of flash memories on scaled and multilevel flash cell design

This paper, for the first time, describes the analytical expressions which explicitly relate single-cell characteristics to Flash array behaviour including statistical consideration. Since the bitline leakage current caused by over-erased cells and/or broad threshold voltage (Vt) distribution generates read/verify circuitry malfunctions and a degraded programming due to voltage drop, and charge-pump circuitry failure, this leakage are extensively analyzed to find the optimum operation biases, array Vt design, their allowed variations and bitline segmentation in the scaled multilevel cell generation.