An investigation of parallel memetic algorithms for VLSI circuit partitioning on multi-core computers

Circuit-partitioning is one of the most important, but time-consuming steps, in the VLSI design flow. In this paper, we investigate six different parallel Memetic Algorithms for solving the circuit-partitioning problem. Each parallel implementation uses a global shared-memory to exchange information, and seeks to reduce runtime by exploiting the multiple cores available in today´s commodity hardware. When tested with the widely used ACM/SIGDA benchmark suite, our empirical results show that near-linear speedups for all six MAs can be achieved, while still producing high-quality solutions.