Hardware aspects of fixed relay station design for OFDM(A) based wireless relay networks

Hardware aspects of infrastructure based (i.e., fixed) relay station design with focus on digital baseband processing in OFDM(A) based systems are investigated. A novel architecture for the digital baseband processor for fixed relay stations is proposed to minimize the relay complexity and the implementation cost. Two methods of signal forwarding -amplify and forward (AF) and -decode and forward (DF) are developed and implemented on FPGA, exploiting parallel processing and a pipelined system architecture. In contrast to common heuristic conclusions existing in the literature, we conclude that the AF based implementation introduces significant hardware complexity resulting from high memory usage. On the other hand, the DF implementation requires higher clocking frequencies, making it more power-consuming as compared to AF-based relaying.