A nanoelectronic memory array design with improved performance

Author

Barua, Mrinmoy ; Abid, Z.

Author_Institution

Dept. of Electr. & Comput. Eng., Western Ontario Univ., London, ON

fYear

2008

fDate

4-7 May 2008

Abstract

We present the design of a nanoelectronic memory array compatible with molecular switch (nanodevice) electrical characteristics. The proposed transmission gate based CMOL (hybrid CMOS / molecular) memory cell surmounts the operational difficulties facing the existing CMOL cell. The control circuitry with improved multiplexer design is introduced in this paper. HSPICE simulation shows that the required voltage levels can be achieved by using the proposed designs. Yield improvement through replacing the defective cell with a free cell can be achieved using a proposed algorithm. Moreover, the proposed memory cell has the same area as the existing CMOL inverter cells allowing easier implementation of both logic and memory circuits on the same chip.

Keywords

CMOS memory circuits; integrated circuit design; molecular electronics; CMOL inverter cells; HSPICE simulation; memory cell; molecular switch; nanoelectronic memory array design; transmission gate based CMOL; CMOS logic circuits; CMOS technology; Circuit simulation; Logic circuits; Logic devices; Nanoscale devices; Pulse inverters; Silicon; Switches; Voltage; CMOL memory cell; Molecular switch; Nanodevices; Nanotechnology;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2008. CCECE 2008. Canadian Conference on

Conference_Location

Niagara Falls, ON

ISSN

0840-7789

Print_ISBN

978-1-4244-1642-4

Electronic_ISBN

0840-7789

Type

conf

DOI

10.1109/CCECE.2008.4564570

Filename

4564570