Power aware design of superscalar architecture for high performance DSP operations

In this paper a methodology for architectural level power optimization of a superscalar processor is proposed. The optimization is targeted at high performance real-time DSP operations. Sample rate conversion operation in software defined radios has been taken as an exemplar operation. Various superscalar configurations have been obtained through a systematic procedure. SimpleScalar architecture modeling tool has been used for simulation along with its power estimation extension - Wattch. Overall performance gain of more than 100 percent has been achieved while meeting all operating constraints.