Designing a hardware accelerator for vector quantization as a component of a SoPC

A flexible accelerator hardware for full-search vector quantization (VQ) has been developed as a component for a system on a programmable chip (SOPC) to use in real-time image compression and recognition applications. In this system, the number of elements for each codeword and the number of codewords in the system can be changed easily for different applications with the use of an embedded CPU. The architecture allows to use look up tables (LUTs), single-instruction multiple-data (SIMD) and two-stage pipeline architecture. This leads to high speed operation which is quite suitable for real-time applications. In addition, an improved method for image compression using VQ was developed using this architecture. The technique was implemented and successfully tested in an Altera Stratix II DSP FPGA Development Kit.