VLSI Design and Implementation of a High-Speed Multicast Switch Fabric

This paper presents the VLSI design and implementation of a new cell-based high-speed multicast switch fabric using the 0.18 mum CMOS technology. Using distributed control, multistage interconnection network structure, and modular design, the multicast balanced gamma (BG) switch features a scalable, high performance architecture for unicast, multicast and combined traffic under both uniform and non-uniform traffic conditions. The BG switch follows predominantly an output-buffered architecture and utilizes a self-replication mechanism for multicast traffic switching. In the paper, we discuss in detail the front-end design issues of the switch using the ASIC design flow recommended by the Canadian Microelectronics Corporation (CMC). Synthesized results are provided for measures of circuit complexity and timing