A High-Gain, Low-Noise, +6dBm PA in 90nm CMOS for 60-GHz Radio

Author

Khanpour, M. ; Voinigescu, S.P. ; Yang, M.T.

Author_Institution

Univ. of Toronto, Toronto

fYear

2007

fDate

14-17 Oct. 2007

Firstpage

1

Lastpage

4

Abstract

A 60-GHz power amplifier with 14 dB gain, 5 dB simulated noise figure, and a saturated output power of +6 dBm was fabricated in a 90 nm GP process with a 9-metal digital back end. The amplifier employs two cascode stages and a common-source output stage with inductive degeneration. It has a power-added-efficiency of 6% while consuming 45 mW from a 1.5-V supply. The robustness and repeatability of the small signal and large signal performance were characterized across dies, power supply voltage, and over temperature up to 125degC. The design was also scaled to 85 GHz in 65 nm CMOS with +5 dBm P_sat.

Keywords

CMOS analogue integrated circuits; integrated circuit design; low noise amplifiers; millimetre wave power amplifiers; CMOS; cascode stages; common-source output stage; frequency 60 GHz; gain 14 dB; high-gain amplifier; inductive degeneration; low-noise amplifier; noise figure; noise figure 5 dB; power amplifier; voltage 1.5 V; wavelength 90 nm; CMOS technology; Equivalent circuits; Germanium silicon alloys; Heterojunction bipolar transistors; Low-noise amplifiers; Power amplifiers; Power generation; Radiofrequency amplifiers; Silicon germanium; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Compound Semiconductor Integrated Circuit Symposium, 2007. CSIC 2007. IEEE

Conference_Location

Portland, OR

Print_ISBN

978-1-4244-1022-4

Type

conf

DOI

10.1109/CSICS07.2007.29

Filename

4384409