A pseudo-noise code synchronizer circuit design for DS-DQPSK spread spectrum receiver with 0.6 (suμm) CMOS

In this paper a pseudo-noise code synchronizer circuit using for DS-DQPSK spread spectrum receiver for audio applications is designed. It is implemented with 0.6 micron technology of MOSIS Company by use of serial method. The synchronous and asynchronous circuits are used in control unit. As a result, this circuit doesnpsilat need many control clock pulses and its clock pulse generator unit is very simple and easily is implemented. Then, this control unit decreases dissipated power. For reason of using pipeline arithmetic units, we can reach to high speeds. The dissipated power of circuit is decreased because of using 3.3 volts power supply, pipeline arithmetic units, having small fan-out in each multiplier cell, using delay buffers instead of D flip-flops and so on. For transistor implementation of this circuit, TSPC logic is used. By using simulator, transistor sizes are adjusted for suitable performance, speed increasing and dissipated power decreasing without any difference sizes in similar units. By using of these logic and technology, area of circuit decreases very much. The total dissipated power is 50 mW in 300 kb/s input bit rate. This input bit rate proper for digitally audio and video transmission.