VHDL design and FPGA implementation of weighted majority logic decoders

In this work, we propose a design and FPGA (Field Programmable Gate Arrays) implementation of two parallel architectures for majority logic decoder of low complexity for high data rate applications, These architectures are hard decision architecture (Hard in - Hard out (HIHO)) and the SIHO threshold decoding. The code used is the Difference Set Cyclic code (DSC (21, 11)). The VHDL (Very high speed integrated circuit Hardware Description Language) design and the synthesis of such architecture shows such decoders can achieve high data rate with low complexity.