A method for register allocation to loops in multiple register file architectures

Multiple instruction issue processors place high demands on register file bandwidth. One solution to reduce this bottleneck is the use of multiple register files. Register allocation for these architectures then becomes exceedingly important as spill code increases memory bandwidth demands and decreases performance, especially within loops. Previously, we have addressed the issue of finding an optimal allocation of variables to registers within loops for a consolidated register file model. In this paper, we extend that work to architectures where the available registers have been partitioned into multiple banks. Experimental results demonstrate that, while the optimal algorithm may be computationally prohibitive, heuristic versions obtain acceptable performances