DocumentCode :
2133088
Title :
An architecture of high performance cluster network: Maestro2
Author :
Aoki, Keiichi ; Yamagiwa, Shinichi ; Ono, Masaaki ; Wada, Kazuyoshi ; Campos, Luis Miguel
Author_Institution :
Inst. of Inf. Sci. & Electron., Tsukuba Univ., Ibaraki, Japan
Volume :
2
fYear :
2003
fDate :
28-30 Aug. 2003
Firstpage :
784
Abstract :
Cluster computers have become the platform of choice to run high performance parallel computing applications. However, most cluster computers use conventional wide-area network technologies to interconnect the individual processing elements. Therefore, there is a disparity between the wide-area network technologies used and the network technology required by cluster computing, leading to a severe degradation in performance. Maestro network technology attempts to solve this disparity. This paper describes improvements to the basic Maestro architecture. In particular it describes a new technique used by Maestro2 (continuous network burst) and shows its impact in the overall performance of Maestro cluster networks.
Keywords :
parallel processing; workstation clusters; Maestro2 network technology; cluster computer; continuous network burst; high performance cluster network architecture; parallel computing application; Computer architecture; Computer networks; Degradation; Error correction; High performance computing; Network interfaces; Out of order; Switches; Throughput; Wide area networks;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications, Computers and signal Processing, 2003. PACRIM. 2003 IEEE Pacific Rim Conference on
Print_ISBN :
0-7803-7978-0
Type :
conf
DOI :
10.1109/PACRIM.2003.1235898
Filename :
1235898
Link To Document :
بازگشت