Low power implementation of linear phase FIR filters for single multiplier CMOS based DSPs

Recently, a new scheme for the single multiplier implementation of low power digital filters on CMOS-based DSPs was presented. In this paper the scheme is generalised to include linear phase FIR filters (LPFIRs) and its implementation is investigated with two common methods of LPFIR realisation structures. The paper also describes an effective framework which combines layout, timing, and capacitive information, for the evaluation of power consumption for FIR filters. New results are provided which demonstrate up to 85% reduction in overall power consumption. The paper discusses the generalisation of the scheme to LPFIRs and the effects of added overheads, describes the evaluation environment, and provides comprehensive results which show the effectiveness of the scheme as a generic power saving framework for the implementation of FIR filters exploiting coefficient symmetry, where it exists, without the need for specialised realisation structures