A low power and high speed PPM design for ultra wideband communications

This paper describes the design of a high speed Pulse Position Modulator (PPM) in the 90 nm CMOS process, targeted at ir-UWB applications. The PPM design presented in this work is shown to have single cycle latency at 500 MHz of operation and consumes less than 4 mW of DC power. In order to achieve single cycle latency, novel hierarchical delay line architecture is implemented in the design. To control process, temperature, and supply voltage variation impact on the delay line, a Delay Locked Loop (DLL) is implemented with the PPM design. The total power consumption of the PPM with the DLL circuit is 7.5 mW.