Analysis of Random Telegraph Noise in 45-nm CMOS Using On-Chip Characterization System

An on-chip variability characterization system implemented in a 45-nm CMOS process is used for direct time-domain measurements of random telegraph noise (RTN) in small-area devices. A procedure for automated extraction of RTN parameters from large volumes of measured data is developed. Statistics for number of traps, $N_{T}$, and single-trap amplitudes, $Delta V_{rm{th}}$, are studied across device polarity, bias, and gate area. A Poisson distribution is used to model $N_{T}$ and a log-normal distribution is used to model $Delta V_{rm{th}}$. The scaling of the two statistics across gate dimensions is discussed; the expected value of $N_{T}$ is shown to scale with $(L-{Delta}L)^{-1}$ , whereas the expected value of $Delta V_{rm{th}}$ is shown to scale with $W^{-1}(L-{Delta}L)^{-0.5}$. The two statistics are combined in a compact RTN probabilistic model representing the statistics of the overall $Delta V_{rm{th}}$ fluctuations because of RTN. This model is demonstrated to give accurate predictions of the tails of the measured RTN distributions at the 95th percentile level, which scale with $W^{-1}(L-{Delta}L)^{-1.5}$. A comparison between nMOS and pMOS devices shows that pMOS devices exhibit both a higher average number of traps and a larger average single-trap $Delta V_{rm{th}}$ amplitude, leading to a comparatively larger overall impact of RTN.