• DocumentCode
    2134210
  • Title

    Software techniques for improving MPP bulk-transfer performance

  • Author

    Brewer, Eric A. ; Gauthier, Paul ; Fox, Armando ; Schuett, Angela

  • Author_Institution
    California Univ., Berkeley, CA, USA
  • fYear
    1996
  • fDate
    15-19 Apr 1996
  • Firstpage
    406
  • Lastpage
    412
  • Abstract
    Brewer & Kuszmaul (1994) demonstrated how barriers and traffic interleaving can alleviate the problem of bulk-transfer performance degradation on the Thinking Machines CM-5 massively parallel processor (MPP) by exploiting the observation that one-on-one communication avoids network congestion. We apply and extend these techniques on the Intel Paragon and MIT Alewife machines. Because these machines lack the CM-5´s fast hardware support for barriers, we introduce a token-passing scheme that avoids barriers while maintaining one-on-one communication. We also introduce a new algorithm-distributed dynamic scheduling-that brings Brewer & Kuszmaul´s observations to bear on irregular traffic patterns by massaging traffic into a sequence of near-permutations at runtime, without requiring any preprocessing or global state. The measured performance of our algorithm exceeds that of traffic interleaving (the most effective technique proposed by Brewer & Kuszmaul) on all three platforms, and is comparable to the performance of static scheduling, which requires preprocessing and global state
  • Keywords
    parallel machines; performance evaluation; processor scheduling; software performance evaluation; telecommunication traffic; Intel Paragon; MIT Alewife machine; Thinking Machines CM-5; algorithm performance; barriers; bulk-transfer performance; distributed dynamic scheduling; global state; irregular traffic patterns; massively parallel processor; near-permutations; network congestion; one-on-one communication; preprocessing; software techniques; static scheduling; token-passing scheme; traffic interleaving; traffic massaging; Bandwidth; Degradation; Delay; Dynamic scheduling; Hardware; Heuristic algorithms; Interleaved codes; Runtime; Scheduling algorithm; Software performance; Telecommunication traffic;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel Processing Symposium, 1996., Proceedings of IPPS '96, The 10th International
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    0-8186-7255-2
  • Type

    conf

  • DOI
    10.1109/IPPS.1996.508088
  • Filename
    508088