• DocumentCode
    2134553
  • Title

    Wiring space estimation for ECL gate arrays

  • Author

    Laymoun, Samir

  • Author_Institution
    Nat. Semicond., Santa Clara, CA, USA
  • fYear
    1989
  • fDate
    18-19 Sep 1989
  • Firstpage
    27
  • Lastpage
    29
  • Abstract
    An empirical formula that predicts the wiring tracks to be supplied for emitter-coupled-logic (ECL) gate arrays is derived, and factors that influence wiring requirements are explored. The relationship between supplied tracks and the number of cells/gates is a power function. The concept of gate equivalence is introduced to provide a common basis for comparing the different arrays, and a method for calculating the gate equivalence is proposed
  • Keywords
    bipolar integrated circuits; cellular arrays; circuit layout; emitter-coupled logic; logic arrays; logic design; ECL gate arrays; emitter-coupled-logic; gate equivalence; logic IC layout design; wiring space estimation; wiring tracks; Degradation; Equations; Integrated circuit interconnections; Logic arrays; Logic functions; Logic gates; Resistors; Routing; Wires; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Bipolar Circuits and Technology Meeting, 1989., Proceedings of the 1989
  • Conference_Location
    Minneapolis, MN
  • Type

    conf

  • DOI
    10.1109/BIPOL.1989.69454
  • Filename
    69454
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2134553