A multiprocessor server with a new highly pipelined bus

We explore the design issues of a shared bus with a pipelined protocol, so called HiPi+Bus, which is implemented for a multiprocessor server. The characteristics and design parameters for the HiPi+Bus are described. From the viewpoint of a pipelined bus, a block transfer is no good because it involves a complex and unbalanced pipeline. However it is requested by a local cache memory of which the line size tends to be increased. To get the best performance and compensate unbalanced data transfer caused by block transfer a responder queue for the bus interface is also proposed. According to the simulation results, the HiPi+Bus, with the help of the responder queue, can provide a balanced service for more than 16 processors, which is important in running commercial applications. The HiPi+Bus is implemented for the TICOM III, a successor of the TICOM II which is the main server of the national administrative information network in Korea