Title :
Development of parallel type multi-stage interference canceller for W-CDMA
Author :
Yoshida, Shousei ; Ishii, Naoto ; Mizuguchi, Hironori ; Ushirokawa, Akihisa
Author_Institution :
C&C Media Res. Labs., NEC Corp., Kawasaki, Japan
Abstract :
This paper describes a developed W-CDMA base station testbed with a practical multi-stage interference canceller, which is processed by high-speed digital signal processing cards. The multi-stage canceller features a parallel structure with a cancellation control factor, which can make the parallel cancelling operation stable. A laboratory experiment demonstrates that the developed interference canceller has a high cancelling capability and near-far resistance even when the interference (2 users) power is 9 dB higher than the desired user. The development and experiment proves that this multistage canceller is feasible and effective technology for W-CDMA performance enhancement
Keywords :
broadband networks; code division multiple access; digital signal processing chips; interference suppression; land mobile radio; parallel processing; radio networks; radiofrequency interference; W-CDMA base station testbed; W-CDMA performance enhancement; cancellation control factor; high-speed digital signal processing cards; interference power; laboratory experiment; near-far resistance; parallel structure; parallel type multi-stage interference canceller; Adaptive arrays; Base stations; Channel estimation; Delay; Demodulation; Digital signal processing; Interference cancellation; Laboratories; Multiaccess communication; Testing;
Conference_Titel :
Vehicular Technology Conference Proceedings, 2000. VTC 2000-Spring Tokyo. 2000 IEEE 51st
Conference_Location :
Tokyo
Print_ISBN :
0-7803-5718-3
DOI :
10.1109/VETECS.2000.851227
